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This section is currently based solely on the work by Mark Sokos.
This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only, and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects.
For a copy of the full PCI standard, contact:PCI Special Interest Group (SIG)
Clock. 33 MHz maximum.
Command, Byte Enable.
Used to indicate whether the cycle is an address phase or a data phase.
Initialization Device Select
Used to manage resource locks on the PCI bus.
Request. Requests a PCI transfer.
Grant. indicates that permission to use PCI is granted.
Parity. Used for AD0-31 and C/BE0-3.
System Error. Indicates an address parity error for special cycles or a system error.
Asserted by Target. Requests the master to stop the current transfer cycle.
Test Data Input
Test Data Output
Test Mode Select
Test Logic Reset
The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinitely, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space).
The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector.
The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.
|1100||Multiple Memory Read|
|1101||Dual Address Cycle|
|1111||Memory Write and Invalidate|
The three basic types of transfers are I/O, Memory, and Configuration.
___ ___ ___ ___ ___ ___ CLK ___| |___| |___| |___| |___| |___| |___ _______ _________ FRAME |_________________________________| ______ _______ ______ ______ ______ AD -------<______><_______><______><______><______>--- Address Data1 Data2 Data3 Data4 ______ _______________________________ C/BE -------<______><_______________________________>--- Command Byte Enable Signals ____________ ___ IRDY |_________________________________| _____________ ___ TRDY |________________________________| ______________ ___ DEVSEL |_______________________________|
PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK.
   ___ ___ ___ ___ ___ ___ ___ ___ CLK ___| |___| |___| |___| |___| |___| |___| |___| |__ _______ _________ FRAME |________________________________________________| A B C ______ ______________ ______ _____________ AD -------<______>---------<______________><______><_____________>--- Address Data1 Data2 Data3 ______ ______________________________________________ C/BE -------<______><______________________________________________>--- Command Byte Enable Signals Wait ____________ _____ ___ IRDY |__________________________________| |_______| Wait Wait ______________________ ______ ___ TRDY |_______| |_______________________| ______________ ___ DEVSEL |______________________________________________|
PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labelled A, B, and C.
The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines.
|0x0002||x86 Specific Code|
|0x0003 to 0xFFFF||Reserved|
Input/Output device read or write operation. The AD lines contain a byte address (AD0 and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror themselves throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots.
The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must be written first.
A read or write to the system memory space. The AD lines contain a doubleword address. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid.
A read or write to the PCI device configuration space, which is 256 bytes in length. It is accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the remaining AD lines are not used.
Address Bit 32 16 15 0 00 Unit ID | Manufacturer ID 04 Status | Command 08 Class Code | Revision 0C BIST | Header | Latency | CLS 10-24 Base Address Register 28 Reserved 2C Reserved 30 Expansion ROM Base Address 34 Reserved 38 Reserved 3C MaxLat|MnGNT | INT-pin | INT-line 40-FF available for PCI unit
This is an extension of the memory read bus cycle. It is used to read large blocks of memory without caching, which is beneficial for long sequential memory accesses.
Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical address exists. The least significant portion of the address is placed on the AD lines first, followed by the most significant 32 bits. The second address cycle also contains the command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O address space, although this is not available on Intel based PCs due to limitations of the CPU.
This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a cache line. It is more efficient than normal memory read bursts for a long series of sequential memory accesses.
This indicates that a minimum of one cache line is to be transferred. This allows main memory to be updated, saving a cache write-back cycle.
This section is under construction.
This section is under construction.
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