50 PIN ?? at the Computer.
| Pin |
Name |
Dir |
Description |
| 1 |
/CS1 |
 |
Memory Read in addresses 4000-7FFF |
| 2 |
/CS2 |
 |
Memory Read in addresses 8000-BFFF |
| 3 |
/CS12 |
 |
Memory Read in addresses 4000-BFFF |
| 4 |
/SLTSL |
 |
Low when Slot 2 (cartridge slot) is selected |
| 5 |
n/c |
- |
Not connected. |
| 6 |
/RFSH |
 |
Refresh signal from CPU |
| 7 |
/WAIT |
 |
OC, Tells CPU to wait. Refresh signal is not maintained |
| 8 |
/INT |
 |
OC, Requests a interrupt to CPU (call to addr 38h) |
| 9 |
/M1 |
 |
CPU fetches first part of instruction from memory. |
| 10 |
/BUSDIR |
 |
NC, was used to control the data direction. |
| 11 |
/IORQ |
 |
I/O request signal. (Address=Port) |
| 12 |
/MREQ |
 |
Memory request signal. (Address=Address) |
| 13 |
/WR |
 |
Write signal (strobe) |
| 14 |
/RD |
 |
Read signal (strobe) |
| 15 |
/RESET |
 |
Reset |
| 16 |
n/c |
- |
Not connected. |
| 17 |
A0 |
 |
Address 0 |
| 18 |
A1 |
 |
Address 1 |
| 19 |
A2 |
 |
Address 2 |
| 20 |
A3 |
 |
Address 3 |
| 21 |
A4 |
 |
Address 4 |
| 22 |
A5 |
 |
Address 5 |
| 23 |
A6 |
 |
Address 6 |
| 24 |
A7 |
 |
Address 7 |
| 25 |
A8 |
 |
Address 8 |
| 26 |
A9 |
 |
Address 9 |
| 27 |
A10 |
 |
Address 10 |
| 28 |
A11 |
 |
Address 11 |
| 29 |
A12 |
 |
Address 12 |
| 30 |
A13 |
 |
Address 13 |
| 31 |
A14 |
 |
Address 14 |
| 32 |
A15 |
 |
Address 15 |
| 33 |
D0 |
 |
Data 0 |
| 34 |
D1 |
 |
Data 1 |
| 35 |
D2 |
 |
Data 2 |
| 36 |
D3 |
 |
Data 3 |
| 37 |
D4 |
 |
Data 4 |
| 38 |
D5 |
 |
Data 5 |
| 39 |
D6 |
 |
Data 6 |
| 40 |
D7 |
 |
Data 7 |
| 41 |
GND |
 |
Ground |
| 42 |
CLOCK |
 |
CPU clock, 3.579 MHz |
| 43 |
GND |
 |
Ground |
| 44 |
SW1 |
- |
NC, Insert/remove detection for protection |
| 45 |
+5V |
 |
+5 VDC (300mA max /slot) |
| 46 |
SW2 |
- |
NC, Insert/remove detection for protection |
| 47 |
+5V |
 |
+5 VDC (300mA max /slot) |
| 48 |
+12V |
 |
+12 VDC (50mA max /slot) |
| 49 |
SOUNDIN |
 |
Sound input (-5dBm) |
| 50 |
-12V |
 |
-12 VDC (50mA max /slot) |